The present invention relates to semiconductor devices and methods of forming thereof, more particularly, to a semiconductor device having a field effect transistor and a method of forming thereof.
In semiconductor devices, a field effect transistor (hereinafter referred to as “a transistor”) includes source/drain regions that are formed apart from each other in the substrate and the gate electrode is disposed on a channel region between the source/drain regions with a gate oxide layer interposed therebetween.
In general, the gate electrode includes doped polysilicon. As the doped polysilicon is formed by a very simple method, and has a good interfacial characteristic with the gate oxide layer formed of a silicon oxide layer, it is widely used as a gate electrode of a transistor.
As the degree of integration for semiconductor devices becomes higher, the line-width of a gate electrode gradually decreases. Accordingly, as the resistance of the gate electrode increases, the operational speed of the transistor becomes slower. In order to overcome this problem, a method for forming a gate electrode with polycide has been suggested. The polycide consists of doped polysilicon and tungsten silicide, which are sequentially stacked. A transistor including a gate electrode formed of polycide is disclosed in Korean Laid-open Patent Publication No. 2004-37957.
FIG. 1 is a schematic view illustrating a field effect transistor of a conventional semiconductor device.
With reference to FIG. 1, a gate oxide layer 2, a doped polysilicon pattern 3 and a tungsten silicide pattern 4 are sequentially stacked on an active region of a semiconductor substrate 1. The tungsten silicide pattern 4 has a resistivity lower than the dope polysilicon pattern 3. Source/drain regions 6 are formed at the active region at both sides of a gate electrode 5.
The gate electrode 5 includes the doped polysilicon pattern 3 and the tungsten silicide pattern 4 formed on the doped polysilicon pattern 3. Due to the low resistivity of the tungsten silicide pattern 4, the resistance of the gate electrode 5 is decreased and the operational speed of a transistor may become fast.
However, as the current state of the art requires a semiconductor device having a minimum line-width of less than 100 nm, although the gate electrode 5 is formed of polycide, the resistance of the gate electrode 5 will increase due to the decreased line-width, and the operational speed of the transistor may gradually decrease. In addition, as the length of the channel region below the gate electrode 5 decreases, thereby inducing a short channel effect etc., it leads to a punch through characteristic between the source/drain regions 6. Accordingly, there are many problems in scaling down a transistor due to the above problems.
In addition, the gate electrode 5 is formed with a patterning process including a plasma etching process. Accordingly, the gate oxide layer 2 below the edges of the gate electrode 5 may be plasma-damaged. As a result, the characteristics of a transistor may deteriorate.